1. Field of the Invention
The present invention relates to a semiconductor storage device and, particularly, to a semiconductor storage device that is static random access memory (SRAM).
2. Description of Related Art
SRAM is one kind of semiconductor storage devices. FIG. 5 shows an example of a typical SRAM circuit as a related art. The SRAM 100 shown in FIG. 5 includes bit lines DT1 and DB1 to DTn and DBn. Memory cells F1 to Fn are connected respectively to the bit lines DT1 and DB1 to DTn and DBn.
Each of the memory cells F1 to Fn includes drive transistors Tr10 and Tr11, load transistors Tr20 and Tr21, and transfer transistors Tr30 and Tr31. Data that is stored in each of storage nodes A and B, which are formed at connection points between the drive transistors and the load transistors, is transferred to the bit lines DT1 and DB1 to DTn and DBn through the transfer transistors, thereby reading the data.
The operation of the SRAM is to write and read data by repeating a precharge period and a discharge period of the bit lines.
For example, the case of selecting the memory cell F1 and writing data “0” into the selected memory cell F1 is as follows. First, a precharge circuit that precharges the bit lines DT1 and DB1 to High level is turned off, and thereby the bit lines DT1 and DB1 enters a high impedance state. If, in this state, a word line WLX is set to High level, the transistors Tr30 and Tr31 are turned on, so that the bit lines DT1 and DB1 are connected to the storage nodes A and B. Because the data “0” is to be written into the memory cell F1, the bit line DT1 is set to Low level, and the bit line DB1 is set to High level. The bit line DT1 is thereby discharged. Accordingly, the storage node A becomes Low level, and the storage node B becomes High level, and thereby data writing is performed. Finally, the word line WLX is set to Low level so that the transistors Tr30 and Tr31 are turned off, and thereby data writing is completed. After that, the precharge circuit is turned on, and the bit lines DT1 and DB are precharged. Therefore, the bit line DT1 is charged to High level again.
On the other hand, the case of selecting the memory cell F1 and reading data “0” stored in the selected memory cell F1 is as follows. First, the precharge circuit that precharges the bit lines DT1 and DB1 to High level is turned off, and thereby the bit lines DT1 and DB1 enter a high impedance state. If, in this state, a word line WLX is set to High level, the transistors Tr30 and Tr31 are turned on, so that the bit lines DT1 and DB1 are connected to the storage nodes A and B. The storage node A serves as an output terminal of an inverter that is composed of the transistors Tr10 and Tr20 and an input terminal of an inverter that is composed of the transistors Tr11 and Tr21. The storage node B serves as an input terminal of the inverter that is composed of the transistors Tr10 and Tr20 and an output terminal of the inverter that is composed of the transistors Tr11 and Tr21. Because the memory cell F1 stores the data “0”, the storage node A stores a Low-level potential and the storage node B stores a High-level potential. Thus, the bit line DT1 is connected to the storage node A, so that the bit line DT1 is discharged. Accordingly, the potential of the bit line DT decreases, and a potential difference from the bit line DT is amplified and read by a sense amplifier (not shown), and thereby data reading is performed. Finally, the word line WLX is set to Low level so that the transistors Tr30 and Tr31 are turned off, and thereby data reading is completed. After that, the precharge circuit is turned on, and the bit lines DT1 and DB are precharged. Therefore, the bit line DT1 is charged to High level again.
In this configuration, however, the memory cells on which data writing and reading are not performed, which are the non-selected memory cells F2 to Fn, are also connected to the same word line WLX as the selected memory cell F1. Therefore, in the non-selected memory cells F2 to Fn, unnecessary discharge and precharge are performed on the bit lines DT2 and DB2 to DTn and DBn that are respectively connected thereto. This causes an increase in power consumption of SRAM.
In light of the above issue, a technique for preventing an increase in power consumption of SRAM is disclosed in Japanese Unexamined Patent Application Publications Nos. 8-7574 and 2006-209877, for example. They describe the SRAM 110 in which a transistor Tr40 is inserted between the transfer transistor Tr30 and the bit line DT and a transistor Tr41 is inserted between the transfer transistor Tr31 and the bit line DB in the memory cell F1 of FIG. 5, as shown in FIG. 6. Further, a Y-decoder 601 controls the potential level of word lines WLY1 to WLYn that are connected to the gates of the transistors Tr40 and T41 and turns on and off the transistors Tr40 and T41 of each memory cell.
FIG. 7 shows a timing chart of the SRAM circuit shown in FIG. 6. It is the timing chart of the operation of writing data “0” into the memory cell F1 and the operation of reading data “0” stored in the memory cell F1. As shown in FIG. 7, the potential of the word line WLX rises to High level and the potential of the word line WLY1 also rises to High level at the same time, so that the transistors Tr30, Tr40, Tr31 and Tr41 of the selected memory cell F1 are turned on. As a result, the storage nodes A and B are connected to the bit lines DT and DB, and thereby data reading and reading are performed.
Because the potentials of the word lines WLY2 to WLYn remain Low level, the transistors Tr40 and Tr41 of the non-selected memory cells F2 to Fn stay off. Thus, discharge and precharge are performed on the bit line DT1 only. Accordingly, discharge of the bit lines that are connected to the non-selected memory cells F2 to Fn is not performed, and the precharge circuit is kept on. This thus eliminates unnecessary discharge and charge of the bit lines connected to the non-selected memory cells, thereby preventing an increase in power consumption of SRAM.
However, in the SRAM circuit shown in FIG. 6, the bit lines DT1 and DB1 to DTn and DBn and the word lines WLY1 to WLYn are formed in parallel with each other on a semiconductor chip. Therefore, a change in the potential of the word line WLY1, for example, causes crosstalk into the bit lines DT1 and DB1, which adversely affects a change in the potentials of the bit lines for data output.
In the SRAM circuit 110, the Y-decoder 601 to which the word lines WLY1 to WLYn are connected and an X-decoder 602 to which the word line WLX is connected start operating at the same time. In such a case, immediately after the potential of the word line WLY1 rises from Low level to High level, the transfer transistors Tr40 and Tr41 that are connected to the word line WLY1 discharge one of the bit lines DT1 and DB1 to reduce the potential according to the stored data in the selected memory cell.
For example, the case of reading data “0” stored in the memory cell F1 described above is as follows. When the potential of the word line WLX rises to High level and the potential of the word line WLY1 also rises to High level at the same time, the potential of the bit line DT1 falls to Low level immediately after that timing. At this time, due to the crosstalk from the word line WLY1 whose potential rises to High level as described above, the potential of the bit line DT1 is hard to fall. Further, due to the crosstalk of the potential of the bit line DT1 falling to Low level into the word line WLY1, the potential of the word line WLY1 is hard to rise.
On the other hand, in the case of writing data “0” into the memory cell F1, a buffer in the Y-decoder 601 changes the potential of the bit line DT1 to Low level. At this time, the crosstalk at the falling of the potential of the bit line DT1 causes the potential of the word line WLY1 to be hard to rise. In this manner, crosstalk occurs between the bit lines DT1 and DB1 to DTn and DBn and the word lines WLY1 to WLYn placed in parallel therewith due to a change in their potentials, causing a delay in rising and falling of the potential level.